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FUJITSU MICROELECTRONICS DATA SHEET
DS04-27261-6E
ASSP for Power Management Applications of Ultra Mobile PC
6ch DC/DC Converter IC for LPIA Platform VR
MB39C308
DESCRIPTION
The MB39C308 is a 6ch DC/DC buck converter LSI, which integrates all of necessary power supplies for UltraMobile PC powered by 2-cell Li-ion battery. And the MB39C308 uses current mode topology with N-channel synchronous rectification to realize high conversion efficiency. The MB39C308 is the Power Management IC supporting the LPIA(Low Power Intel Architecture) which Intel Corporation proposes as the low power consumption platform for UMPC. The CH1 and CH2 are flexible to adopt the output current capability by selection of external FETs and easy to optimize efficiency. The CH3, CH4, CH5 and CH6 integrate the switching FETs capable of high current for downsizing the power supply solution. The MB39C308 uses Fujitsu's LDMOS process technology and supplies all power without dispersing power from a lithium-ion battery.
FEATURES
* * * * * * Input voltage range : 5.5 V to 12.6 V Topology : Current Mode Integrated FET Driver for external MOSFETs : CH1, CH2 Integrated Switching MOSFETs : CH3, CH4, CH5, CH6 Fixed Preset Output Voltage : CH1, CH2, CH5 Selectable Preset Output Voltage : CH3, CH4, CH6 Channel CH1 CH2 CH3 CH4 CH5 CH6 Output voltage 5V 3.3 V 1.8 V/1.5 V 0.9 V/0.75 V 1.5 V 1.1 V/1.05 V Output current 2 A* 4.5 A* Max : 2.7 A Max : 1.5 A Max : 2.5 A Max : 3.5 A Remarks DDR2/DDR3 are selectable. Two values are selectable. (Continued)
* : It is the reference value at the typical EVB.
Copyright(c)2007-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.9
MB39C308
(Continued) * PWM switching frequency
: 0.7 MHz (CH4 : 0.7 MHz/0.35 MHz)
* Various protection - Over current protection (OCP) - Input over voltage protection (IVP) - Output short circuit protection (SCP) - Under voltage lock out protection (UVLO) - Output over voltage protection (OVP) - Over temperature protection (OTP) * POWERGOOD function * Soft start function independent from output loads. * Soft stop function independent from output loads. * High conversion efficiency in wide range of load current. * Packaged in a compact package : PFBGA-208 (9.00 mm x 9.00 mm x 1.30 mm)
APPLICATIONS
* UMPC (Ultra Mobile PC) * MID (Mobile Internet Device) * Mobile equipment
etc.
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MB39C308
PIN ASSIGNMENT
(BOTTOM VIEW)
CH3
NC LX3C LX3A PVDD3G PVDD3D PVDD3A PVDD2
CH2
CB2 LX2
CH1
16 PGND2 PGND1 LX1 CB1 PVDD1 SS1 NC 15
LX3G
LX3D
LX3B
PVDD3H PVDD3E PVDD3B OUT2H OUT2L
FB2
FB1
OUT1L OUT1H
CTL1
CTL2
SS2
AVDD 14
LX3H
LX3E
CB3
PVDD3I PVDD3F PVDD3C
PG1
PG2
PG3
PG4
PG5
PG6
ALLPG
CTL34
AGND
VREF 13
Common
LX3I
LX3F
FB3
CTL5
CTL6
PGND7 12
PGND3GPGND3D PGND3A
FSEL4
DIN
VB 11
PGND3H PGND3E PGND3B
VSEL34 DVSEL6 PVDD7 10
PGND3I PGND3F PGND3C
FB6
PVDD6E PVDD6A 9
PGND4F PGND4C PGND4A
PVDD6I PVDD6F PVDD6B 8
PGND4GPGND4D PGND4B
PVDD6J PVDD6G PVDD6C 7
PGND4H PGND4E
FB4
CB6
PVDD6H PVDD6D 6
CH4
LX4F
LX4C
LX4A
CH6
LX6G
LX6D
LX6A 5
LX4G
LX4D
LX4B
LX6H
LX6E
LX6B 4
Thermal PIn
LX4H LX4E CB4
CH5
FB5 LX5G LX5D
LX6I
LX6F
LX6C 3
PVDD4F PVDD4C PVDD4A PVDD5E PVDD5B
LX5A PGND5GPGND5D PGND5A PGND6H LX6J
PGND6C PGND6A 2
PVDD4G PVDD4D PVDD4B PVDD5F PVDD5C
CB5
LX5H
LX5E
LX5B
PGND5H PGND5E PGND5B PGND6I PGND6F PGND6D PGND6B 1
NC
PVDD4E PVDD5H PVDD5G PVDD5D PVDD5A
LX5I
LX5F
LX5C
PGND5I PGND5F PGND5C PGND6J PGND6G PGND6E
NC
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
(BGA-208P-M02)(156-pin + Thermal 52-pin)
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MB39C308
PIN DESCRIPTIONS
Block Pin Name FB1 PVDD1 CB1 CH1 LX1 OUT1H OUT1L PGND1 FB2 PVDD2 CB2 CH2 LX2 OUT2H OUT2L PGND2 FB3 PVDD3A to PVDD3I CB3 CH3 LX3A to LX3I PGND3A to PGND3I FB4 PVDD4A to PVDD4G CB4 CH4 LX4A to LX4H PGND4A to PGND4H I/O I O O O I O O O I O Description CH1 Error amplifier input pin, being connected to output of CH1. Power supply pin of the CH1 output block. Internal power supply pin of the CH1 gate driver block. CH1 inductor connection pin. CH1 High-side N-ch FET drive output pin. CH1 Low-side N-ch FET drive output pin. Ground pin of the CH1 output block. CH2 Error amplifier input pin, being connected to output of CH2. Power supply pin of the CH2 output block. Internal power supply pin of the CH2 gate driver block. CH2 inductor connection pin. CH2 High-side N-ch FET drive output pin. CH2 Low-side N-ch FET drive output pin. Ground pin of the CH2 output block. CH3 Error amplifier input pin, being connected to output of CH3. Power supply pins of the CH3 output block. Internal power supply pin of the CH3 gate driver block. CH3 inductor connection pins.
I O
Ground pins of the CH3 output block. CH4 Error amplifier input pin, being connected to output of CH4. Power supply pins of the CH4 output block. Internal power supply pin of the CH4 gate driver block. CH4 inductor connection pins.
Ground pins of the CH4 output block. (Continued)
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MB39C308
Block
Pin Name FB5 PVDD5A to PVDD5H CB5
I/O I O
Description CH5 Error amplifier input pin, being connected to output of CH5. Power supply pins of the CH5 output block. Internal power supply pin of the CH5 gate driver block. CH5 inductor connection pins.
CH5
LX5A to LX5I PGND5A to PGND5I FB6 PVDD6A to PVDD6J CB6
I O
Ground pins of the CH5 output block. CH6 Error amplifier input pin, being connected to output of CH6. Power supply pins of the CH6 output block. Internal power supply pin of the CH6 gate driver block. CH6 inductor connection pins.
CH6
LX6A to LX6J PGND6A to PGND6J CTL1 CTL2 CTL34 CTL5 CTL6 PG1 PG2 PG3 PG4 PG5 PG6 ALLPG
I I I I I O O O O O O O
Ground pins of the CH6 output block. CH1 Control input pin. (L : Standby / H : Normal operation) CH2 Control input pin. (L : Standby / H : Normal operation) CH3 and CH4 control input pin. (L : Standby / H : Normal operation) CH5 Control input pin. (L : Standby / H : Normal operation) CH6 Control input pin. (L : Standby / H : Normal operation) CH1 POWERGOOD output pin. (N-ch MOS open drain output) CH2 POWERGOOD output pin. (N-ch MOS open drain output) CH3 POWERGOOD output pin. (N-ch MOS open drain output) CH4 POWERGOOD output pin. (N-ch MOS open drain output) CH5 POWERGOOD output pin. (N-ch MOS open drain output) CH6 POWERGOOD output pin. (N-ch MOS open drain output) POWERGOOD output pin (The ALLPG pin outputs "H", When channels CH3, CH4, CH5 and CH6 are the power good). CH4 switching frequency setting pin. FSEL4 = "H" : 700 kHz FSEL4 = "L" : 0.35 MHz (Shown in the " ELECTRICAL CHARACTERISTICS" ) (Continued)
Common
FSEL4
I
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MB39C308
(Continued) Block
Pin Name VSEL34
I/O I
Description Preset output voltage setting pin for CH3/CH4. VSEL34 = "H" : Vout_CH3 =1.8 V, Vout_CH4 = 0.9 V VSEL34 = "L" : Vout_CH3 =1.5 V, Vout_CH4 = 0.75 V Preset output voltage setting pin for CH6 dynamically. DVSEL6 = "H" : Vout_CH6 = 1.1 V DVSEL6 = "L" : Vout_CH6 = 1.05 V Soft-Start and Soft-Stop time setting pin (Shown in the " DESCRIPTION OF SOFT-START AND SOFT-STOP OPERATION * Soft-Start/Soft-Stop time (tson/tsoff) Setting Conditions"). Bias voltage output pin for bootstrap and low-side N-ch gate driver of all channels. Bias voltage input pin for bootstrap. DIN pin should be connected with VB pin. (Shown in the " BLOCK DIAGRAM") Power supply pin of VB block. Ground pin of VB block. Power supply pin for common block. Reference voltage output pin. Ground pin of common block.
DVSEL6 SS1 SS2 Common VB
I
I
O
DIN PVDD7 PGND7 AVDD VREF AGND
I O
6
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MB39C308
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage CB voltage LX voltage CB to LX voltage OUTH voltage OUTL voltage DIN voltage VB voltage VREF voltage CTL voltage VSEL voltage FSEL voltage FB voltage PG voltage SS voltage Package power dissipation Operating ambient temperature Storage temperature Symbol VDD VCB VLX VCBLX VOUTH VOUTL VDIN VVB VVREF VCTL VSEL VFSEL VFB VPG VSS PD Ta TSTG Ta + 25 C Ta = + 85 C Condition AVDD, PVDD1 to PVDD7 pin CB1 to CB6 pin LX1 to LX6 pin CB pin to LX pin OUT1H, OUT2H pin OUT1L, OUT2L pin DIN pin VB pin VREF pin CTL1 to CTL6 pin VSEL34, DVSEL6 pin FSEL4 pin FB1 to FB6 pin PG1 to PG6, ALLPG pin Rating Min -0.3 -0.3 -0.3 -0.3 VLX - 0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 -55 Max + 13.5 + 18.5 VDD +7 VCB +7 +7 +7 +7 + 13.5 +7 +7 +7 +7 +7 2940* 1180* + 85 + 125 Unit V V V V V V V V V V V V V V V mW mW C C
* : See the diagram of " TYPICAL CHARACTERISTICS * Maximum Power Dissipation vs. Operating Ambient Temperature", for the package power dissipation of Ta from + 25 C to + 85 C. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. WARNING: The use of negative voltage below -0.3 Volts on the GND pins (AGND, PGND1 to PGND7) may activate parasitic transistors on the silicon, which can introduce abnormal operation. Connecting the LX pin to either VDD pins (AVDD, PVDD1 to PVDD7) or GND pins (AGND, PGND1 to PGND7) directly may cause permanently damage to the device.
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MB39C308
(Continued) Parameter VB output capacitor VREF output capacitor VREF output current PG input voltage PG sink current CTL input voltage VSEL input voltage FSEL input voltage SS input voltage Symbol CVB CVREF IVREF VPG IPG VCTL VSEL VFSEL VSS VB pin VREF pin VREF pin PG1 to PG6, ALLPG pin PG1 to PG6, ALLPG pin CTL1 to CTL6 pin VSEL34, DVSEL6 pin FSEL4 pin SS1, SS2 pin Condition Value Min -1 Typ 1 4.7 Max 0 6 2 AVDD 6 6 VB Unit F F mA V mA V V V V
* : The MB39C308 is designed with assumed operating conditions, which is 60% of the maximum output current on the each channel and being operated with recommended input voltage range. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
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MB39C308
ELECTRICAL CHARACTERISTICS
(Ta = + 25 C, AVDD = PVDD1 to PVDD7 = 7.2 V) Parameter Reference voltage Reference voltage block [VREF] Line regulation Load regulation Bias voltage Load regulation Threshold voltage Hysteresis width Shutdown temperature Hysteresis width Threshold voltage Release voltage Hysteresis width Oscillation frequency*2 Output on level Control block [CTL1 to CTL6] Output off level Input current Symbol VREF VREF Line VREF Load VVB VB Load VTLH VHU TOTPH TH VIVPH VIVPL VHI AVDD pin AVDD pin AVDD pin CH1 to CH3, CH5, CH6 CH4 : FSEL4 pin = "H" Level CH4 : FSEL4 pin = "L" Level VIH VIL ICTLH ICTLL CTL1 to CTL6 pin CTL1 to CTL6 pin CTL1 to CTL6 pin = 3 V CTL1 to CTL6 pin = 0 V Condition VREF pin = 0 mA AVDD pin = 5.5 V to 12.6 V VREF pin = 0 mA to -1 mA 5.5 V AVDD 12.6 V VB pin = 0 mA VB pin = 0 mA to -1 mA AVDD pin AVDD pin Value Min 2.45 -10 -15 4.8 -15 4.5 0.05 12.6 12.5 0.56 0.28 2 23 Typ 2.5 5 5.0 0.1 + 150*1 + 25*1 13.0 12.85 0.15 0.7 0.35 30 Max 2.55 + 10 + 15 5.2 + 15 5.2 0.4 13.4 13.3 0.84 0.42 0.8 43 1 Unit V mV mV V mV V V C C V V V MHz MHz V V A A
Bias voltage block [VB] Under-voltage lockout protection circuit block [ UVLO ] Over-temperature protection circuit block [OTP]
Input over voltage protection circuit block [IVP]
Oscillator block [OSC]
fosc
(Continued)
12
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MB39C308
(Ta = + 25 C, AVDD = PVDD1 to PVDD7 = 7.2 V) Parameter VSEL34, "H" level Output voltage select block [VSEL34, DVSEL6] VSEL34, "L" level Symbol VLGH VLGL ISELH Input current ISELL Low side threshold voltage Power good detection circuit block [PG1 to PG6, ALLPG] High side threshold voltage Hysteresis width PG output low voltage PG leak current AVDD standby current AVDD power supply current CH1 output voltage PVDD1 standby current VPGL VPGH VH VOL ILKPG IAVDDS IAVDD Vo1 IPVDD1S L1 CH1 efficiency CH1 block [CH1] T1 F1 OUT1H source current Condition VSEL34, DVSEL6 pin VSEL34, DVSEL6 pin VSEL34, DVSEL6 pin = 3 V VSEL34, DVSEL6 pin = 0 V FB1 to FB6 pin PG1 to PG6 pin FB1 to FB6 pin PG1 to PG6 pin PG1 to PG6, ALLPG pin = 1 mA PG1 to PG6, ALLPG pin = 6V CTL1 to CTL6 pin = 0 V, AVDD pin = 12.6 V CTL1 to CTL6 pin = 3 V FB1 pin CTL1 pin = 0 V, PVDD1 pin = 12.6 V 0.05 x Io (Max) < Io < 0.3 x Io (Max) 0.3 x Io (Max) < Io < 0.6 x Io (Max) 0.6 x Io (Max) < Io< Io (Max) Value Min 2 23 Vo x 0.85 Vo x 1.05 4.75 87*3 92*3 92*3 Typ 30 Vo x 0.9 Vo x 1.1 Vo x 0.03 0.1 0.25 5 -400*1 Max 0.8 43 1 Vo x 0.95 Vo x 1.15 0.3 1 1 5.25 15 Unit V V A A V V V V A A mA V A % % % mA
Common block
Duty 5%, CB1 pin = 5 V, IsourceH1 LX1 pin = 0 V, OUT1H pin = 0 V IsinkH1 Duty 5%, CB1 pin = 5 V, LX1 pin = 0 V, OUT1H pin = 5 V
OUT1H sink current
400*1
mA
OUT1L source current
Duty 5%, VB pin = 5 V, IsourceN1 LX1 pin = 0 V, OUT1L pin = 0 V
-400*1
mA
(Continued)
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MB39C308
(Ta = + 25 C, AVDD = PVDD1 to PVDD7 = 7.2 V) Parameter Symbol Condition Duty 5%, VB pin = 5 V, LX1 pin = 0 V, OUT1L pin = 5 V OUT1H pin = -15 mA OUT1H pin = 15 mA OUT1L pin = -15 mA OUT1L pin = 15 mA FB1 pin Io1 RonH1 = 32 m, L = 3.3 H FB1 pin FB1 pin SS1 = SS2 = AGND pin FB2 pin CTL2 pin = 0 V, PVDD2 pin = 12.6 V 0.05 x Io (Max) < Io < 0.3 x Io (Max) 0.3 x Io (Max) < Io < 0.6 x Io (Max) 0.6 x Io (Max) < Io < Io (Max) Value Min 5.9*1 3.4*1 1.19 3.135 87*3 92*3 92*3 Typ 400*1 12 12 12 12 6*1 4.0*1 340 1.4 3.3 - 400 Max 18 18 18 18 6.1*1 4.6*1 1.61 3.465 15 Unit
OUT1L sink current
IsinkN1 ROH1 ROL1 ROH1 ROL1 Vo1 IOCP1 RFB1 SS1 Vo2 IPVDD2S L2
mA V A k ms V A % % % mA
OUT1H on resistance OUT1L on resistance Vo1 output over voltage threshold Vo1 over current limit FB1 input resistance Soft Start time CH2 output voltage PVDD2 standby current
CH1 block [CH1]
CH2 efficiency
T2 F2
OUT2H source current CH2 block [CH2]
Duty 5%, CB2 pin = 5 V, IsourceH2 LX2 pin = 0 V, OUT2H pin = 0 V IsinkH2 Duty 5%, CB2 pin = 5 V, LX2 pin = 0 V, OUT2H pin = 5 V
OUT2H sink current
400
mA
OUT2L source current
Duty 5%, VB pin = 5 V, IsourceN2 LX2 pin = 0 V, OUT2L pin = 0 V IsinkN2 ROH2 ROL2 ROH2 ROL2 Duty 5%, VB pin = 5 V, LX2 pin = 0 V, OUT2L pin = 5 V OUT2H pin = -15 mA OUT2H pin = 15 mA OUT2L pin = -15 mA OUT2L pin = 15 mA
- 400
mA
OUT2L sink current

400 12 12 12 12
18 18 18 18
mA
OUT2H on resistance OUT2L on resistance
(Continued)
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MB39C308
(Ta = + 25 C, AVDD = PVDD1 to PVDD7 = 7.2 V) Parameter Vo2 output over voltage threshold CH2 block [CH2] Vo2 over current limit FB2 input resistance Soft start time Symbol Vo2 IOCP2 RFB2 SS2 FB2 pin IO2 RonH1 = 16 m, L = 3.3 H FB2 pin FB2 pin SS1 = SS2 = AGND pin VSEL34 = "H" Level, FB3 pin VSEL34 = "L" Level, FB3 pin LX3 pin = -100 mA, VGS = 5 V LX3 pin = 100 mA, VGS = 5 V CTL34 pin = 0 V, PVDD3 pin = 12.6 V VSEL34 pin = "H" Level, Vo3 = 1.8 V 0.05 x Io (Max) < Io < 0.3 x Io (Max) VSEL34 pin = "L" Level, Vo3 = 1.5 V 0.05 x Io (Max) < Io < 0.3 x Io (Max) VSEL34 pin = "H" Level, Vo3 = 1.8 V 0.3 x Io (Max) < Io < 0.6 x Io (Max) VSEL34 pin = "L" Level, Vo3 = 1.5 V 0.3 x Io (Max) < Io < 0.6 x Io (Max) VSEL34 pin = "H" Level, Vo3 = 1.8 V 0.6 x Io (Max) < Io < Io (Max) VSEL34 pin = "L" Level, Vo3 = 1.5 V 0.6 x Io (Max) < Io < Io (Max) Condition Value Min Typ Max Unit V A k ms V V m m A
3.894*1 3.96*1 4.026*1 6.7*1 1.19 1.71 1.425 7.9*1 220 1.4 1.8 1.5 65*1 40*1 9.0*1 1.61 1.89 1.575 15
CH3 output voltage
Vo3
High-side FET on-resistance Low-side FET on-resistance PVDD3 standby current
RONH3 RONL3 IPVDD3S
L31
85*3
%
CH3 block [CH3]
L32
82*3
%
T31 CH3 efficiency T32
87*3
%
85*3
%
F31
87*3
%
F32
85*3
%
(Continued)
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MB39C308
(Ta = + 25 C, AVDD = PVDD1 to PVDD7 = 7.2 V) Parameter Vo4 over current limit FB4 input resistance CH4 block [CH4] Soft start time FSEL4, "H" level FSEL4, "L" level FSEL4 input current CH5 output voltage High-side FET on-resistance Low-side FET on-resistance PVDD5 standby current Symbol IOCP4 RFB4 SS4 VFLGH4 VFLGL4 IFSELH4 IFSELL4 Vo5 RONH5 RONL5 IPVDD5S L5 CH5 block [CH5] CH5 efficiency T5 F5 Vo5 output over voltage threshold Vo5 over current limit FB5 input resistance Soft start time VOVP5 IOCP5 RFB5 SS5 Condition Io4, L = 1.5 H,fosc = 700 kHz FB4 pin FB4 pin, SS1 = SS2 = AGND pin FSEL4 pin FSEL4 pin FSEL4 pin = 3 V FSEL4 pin = 0 V FB5 pin LX5 pin = -100 mA, VGS = 5 V LX5 pin = 100 mA, VGS = 5 V CTL5 pin = 0 V, PVDD5 pin = 12.6 V 0.05 x Io (Max) < Io < 0.3 x Io (Max) 0.3 x Io (Max) < Io < 0.6 x Io (Max) 0.6 x Io (Max) < Io < Io (Max) FB5 pin Io5, L = 1.5 H FB5 pin FB5 pin, SS1 = SS2 = AGND pin DVSEL6 = "H" Level, FB6 pin DVSEL6 = "L" Level, FB6 pin LX6 pin = -100 mA, VGS = 5 V LX6 pin = 100 mA, VGS = 5 V CTL6 pin = 0 V, PVDD6 pin = 12.6 V Value Min 1.92*1 1.19 2 23 1.425 82*3 85*3 85*3 1.77*1 2.8*1 1.19 1.045 0.9975 Typ 2.4*1 750 1.4 30 1.5 65*1 40*1 1.8*1 3.5*1 250 1.4 1.1 1.05 61*1 35*1 Max 2.88*1 1.61 0.8 43 1 1.575 15 1.83*1 4.2*1 1.61 1.155 1.1025 15 Unit A k ms V V A A V m m A % % % V A k ms V V m m A
CH6 output voltage
Vo6
CH6 block [CH6]
High-side FET on-resistance Low-side FET on-resistance PVDD6 standby current
RONH6 RONL6 IPVDD6S
(Continued)
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MB39C308
(Continued) (Ta = + 25 C, AVDD = PVDD1 to PVDD7 = 7.2 V) Parameter Symbol Condition DVSEL6 pin = "H" Level, Vo6 = 1.1 V 0.05 x Io (Max) < Io < 0.3 x Io (Max) DVSEL6 pin = "L" Level, Vo6 = 1.05 V 0.05 x Io (Max) < Io < 0.3 x Io (Max) DVSEL6 pin = "H" Level, Vo6 = 1.1 V 0.3 x Io (Max) < Io < 0.6 x Io (Max) DVSEL6 pin = "L" Level, Vo6 = 1.05 V 0.3 x Io (Max) < Io < 0.6 x Io (Max) DVSEL6 pin = "H" Level, Vo6 = 1.1 V 0.6 x Io (Max) < Io < Io (Max) DVSEL6 pin = "L" Level, Vo6 = 1.05 V 0.6 x Io (Max) < Io < Io (Max) DVSEL6 pin = "H" Level, Vo6 = 1.1 V, FB6 pin DVSEL6 pin = "L" Level, Vo6 = 1.05 V, FB6 pin IO6, L = 1.5 H FB6 pin FB6 pin, SS1 = SS2 = AGND pin Value Min Typ Max Unit
L61
80*3
%
L62
80*3
%
T61 CH6 efficiency
82*3
%
T62 CH6 block [CH6] F61
82*3
%
81*3
%
F62
81*3
% V V A k ms
Vo6 output over voltage threshold Vo6 over current limit FB6 input resistance Soft start time
1.298*1 1.32*1 1.342*1 1.239*1 1.26*1 1.281*1 4.0*1 1.19 5.0*1 350 1.4 6.0*1 1.61
VOVP6
IOCP6 RFB6 SS6
*1 : This parameter isn't be specified. This should be used as a reference to support designing the circuits. *2 : FSEL4 pin is typically recommended to set to "H" level for fosc = 700 kHz setting. When Vo4 is preset to 0.75 V, the ON duty becomes so small at high input voltage. Then, there is a case CH4 output regulation becomes worse at light load condition. In that case, please set FSEL4 pin to "L" level for fosc = 350 kHz setting. *3 : This is a reference value, which is evaluated by the recommended EVB circuit. This should be used as a reference to support designing the circuits.
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MB39C308
CHANNEL CONTROL FUNCTION
The each channel is turned on and off depending on the voltage levels at the CTL1 pin, CTL2 pin, CTL34 pin, CTL5 pin and CTL6 pin.
* Channel On/Off Setting Conditions CTL1 CTL2 CTL34 CTL5 CTL6
L H L L L L H L L H L L L H L L L H L L H L L L L H L H L L L L L H H
CH1
OFF ON OFF OFF OFF OFF ON
CH2
OFF OFF ON OFF OFF OFF ON
CH3
OFF OFF OFF ON OFF OFF ON
CH4
OFF OFF OFF ON OFF OFF ON
CH5
OFF OFF OFF OFF ON OFF ON
CH6
OFF OFF OFF OFF OFF ON ON
POWER GOOD FUNCTION
The Power Good function is shown in the following figure. The ALLPG pin and the PGx pins are connected to the open drain of the NMOS, and are used by connecting the resistor. When the CTLx pin is turned on, and the output voltage becomes within 7% of the preset voltage, the PGx pin is changed from "L" to "H". PGx = "H" means the status of Power Good. When the change of the output voltage exceeds 10% of the preset voltage, the PGx pin becomes "L". And when the output voltage becomes within 7% of the preset voltage, the PGx pin becomes "H". Moreover, when all of the channels from CH3 to CH6 are the Power Good, the ALLPG pin becomes "H".
Soft Start
Operation
Soft Stop
CTLx PGx Preset Output Voltage Vox -7% +10% +7% -10% -7%
PGx
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MB39C308
PROTECTION
<1> Under Voltage Lock Out Protection (UVLO) The UVLO prevents IC malfunctions or system damage and the degradation caused by the excessive voltage or instantaneous voltage drop of the power supply voltage (AVDD), bias voltage (VB), internal reference voltage (VREF). The UVLO turns off all the high- and low-side FETs of CH1 to CH6 when the AVDD pin drops below 5.0 V(Typ). The UVLO is released when the AVDD pin is above 5.1 V (Typ). This is the non-latch type protection. <2> Input Over Voltage Protection (IVP) The circuit prevents IC malfunctions or system damage and the degradation caused by the excessive voltage or instantaneous voltage drop of the power supply voltage (AVDD). The IVP turns off all the high- and low-side FETs of CH1 to CH6 when the AVDD pin exceeds 13.0 V(Typ). The IVP is released when the AVDD pin drops below 12.85 V (Typ). This is the non-latch type protection. <3> Over Temperature Protection (OTP) The OTP prevents thermal damages on ICs. The IVP function turns off all the high- and low-side FETs of CH1 to CH6 when the junction temperature exceeds +150 C (Typ). The OPT is released when the temperature drops below +125 C (Typ). This is the non-latch type protection. <4> Output Short Circuit Protection (SCP) The SCP function stops outputting data when the output voltage falls and protects the devices connected to outputs. The SCP timer will start to count when either of output voltages CH1 to CH6 falls due to the output short-circuit to GND or excessive currents. The SCP function starts to operate the latch protection and turns off all the highand low-side FETs when the output voltage continues to fall to 1.4 ms (Typ). Follow either of the steps to release the latch of output short circuit protection. - After all of CTL signals from CH1 to CH6 are set to "L" level, turn on the each CTL signal again. - When the voltage of the AVDD pin is below the threshold voltage of the UVLO, and then the voltage of the AVDD pin becomes higher than the threshold voltage of UVLO again, the each output will start up. <5> Output Over Voltage Protection (OVP) The OVP protects the devices which are connected to outputs when the output voltage rises. When either output voltage of the CH1 to CH6 is higher than 120% of each channel's preset voltage (Typ), the OVP turns off all the high- and low-side FETs of the channels (However, the only CH4 is turned off the high-side FET and turned on the low-side FET. The CH4 logic is different from other channels as it is controlled with PWM). The OVP is released when the output voltage is below 103% of the preset voltage (Typ). This is the non-latch type protection. <6> Over Current Protection (OCP) The OCP function controls the output current. When drain-to-source current excessively increases, the OCP controls the output current to the preset value for each channel. Then, because of the OCP functions, the output voltage usually drops. As a result, the SCP stop the all outputs with the latch setting. The OCP functions only for the corresponding channels only, however, the SCP stops all of the channels in the end.
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DESCRIPTION OF SOFT-START AND SOFT-STOP OPERATION
Soft-start function is featured to avoid inrush current when each channels is turned-on. When the CTL1, CTL2, CTL34, CTL5 and CTL6 are set to "H" level, ramped-up voltage is fed on an inverting input of an error amplifier of a channel. Start-time of the soft-start can be predefined and the start time is kept constant independent from a load of the output of the channels. When the CTL1, CTL2, CTL34, CTL5 and CTL6 are set to "L" level, rampeddown voltage is fed on an inverting input of an error amplifier of a channel then the output voltage goes low. Stop-time of the Soft-stop can be predefined and the stop-time is kept constant independent from a load of the output of the channel. The time of both soft-start and soft-stop can be predefined with combination of the level on the SS1 and the SS2 pins as shown in the "* Soft-Start/Soft-Stop time (tson/tsoff) Setting Conditions", and external capacitors and resistors aren't required * Soft-Start/Soft-Stop time (tson/tsoff) Setting Conditions SS1 pin Connecting to AGND pin Connecting to AGND pin Connecting to AGND pin Connecting to VREF pin Connecting to VREF pin Connecting to VREF pin Connecting to VB pin Connecting to VB pin Connecting to VB pin * : Accuracy : Typ 15% SS2 pin Connecting to AGND pin Connecting to VREF pin Connecting to VB pin Connecting to AGND pin Connecting to VREF pin Connecting to VB pin Connecting to AGND pin Connecting to VREF pin Connecting to VB pin Soft-Start time (tson) (Typ) * 1.4 2.2 2.9 3.5 4.1 5.1 5.9 7.3 8.2 Soft-Stop time (tsoff) (Typ) * 1.4 2.2 2.9 3.5 4.1 5.1 5.9 7.3 8.2 Unit ms ms ms ms ms ms ms ms ms
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(4) When CTL34 is set to "H" or "L".
CTL34
Vo3 (1.8 V/1.5 V) (1.8 V/1.5 V) (CH3 Output) Vo4 (0.9 V/0.75 V) (0.9 V/0.75 V) (CH4 Output)
Vo3 and Vo4 starts its SOFT-START /STOP operation simultaneously.
tson
tsoff
PRESET FUNCTION OF CH3/CH4/CH6 OUTPUT VOLTAGE
The preset output voltage of CH3 and CH4 are selected by VSEL34 pin condition. Please refer the following table. The preset output voltage of CH6 is selected by DVSEL6 pin condition. Please refer the following table. * CH3/CH4/CH6 Preset Output Voltage Conditions CONNECTION VREF VSEL34 DVSEL6 Vo3 = 1.8 V setting Vo4 = 0.9 V setting Vo6 = 1.1 V setting
GND Vo3 = 1.5 V setting Vo4 = 0.75 V setting Vo6 = 1.05 V setting
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MB39C308
TYPICAL CHARACTERISTICS
* Maximum Power Dissipation vs. Operating Ambient Temperature Power Dissipation vs. Operating Ambient Temperature
4 Air flow: 0 m/s
Power Dissipation PD (W)
3
2
1
0 -50 -25 0 +25 +50 +75 +100
Operating Ambient Temperature Ta ( C) The Allowable power dissipation is shown in the "* Maximum Power Dissipation vs. Operating Ambient Temperature". The maximum power dissipation depends on the thermal capability of the given package, and the ambient temperature. Sum of power dissipation of each channel (CH1 to CH6) should not exceed the maximum rating. Expected power loss of the each channel's over load current are shown in the "* Power Loss Curve for each channel". * The condition of the thermal model
Air flow : 0 m/s MB39C308 (9 mm x 9 mm x 1.3 mm)
Printed circuit board (FR4 : 117 mm x 84 mm x 0.8 mm)
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* Power Loss Curve for each channel CH1 Output Current vs. Power Loss
1.8 1.8
CH2 Output Current vs. Power Loss
VIN=7.2 V Vo2=3.3 V Si7212DN (2-para) using Thermal design point External FET loss is excluded.
CH1 Power Loss (W)
CH2 Power Loss (W)
1.5 1.2 0.9
VIN=7.2 V Vo1=5.0 V Si7212DN using
1.5 1.2 0.9 0.6 0.3 0
Thermal design point
0.6 0.3 0
External FET loss is excluded.
0
1
2
3
4
5
0
1
2
3
4
5
CH1 Output Current (A) CH3 Output Current vs. Power Loss
1.8 1.8
CH2 Output Current (A) CH4 Output Current vs. Power Loss
CH3 Power Loss (W)
1.2 0.9
CH4 Power Loss (W)
1.5
VIN=7.2 V Vo3=1.8 V/1.5 V
Vo3=1.5 V Vo3=1.8 V
1.5 1.2 0.9 0.6 0.3 0
VIN=7.2 V Vo4=0.9 V/0.75 V
Vo4=0.9 V Vo4=0.75 V
Thermal design point
0.6 0.3 0
Thermal design point
0
1
2
3
4
5
0
1
2
3
4
5
CH3 Output Current (A) CH5 Output Current vs. Power Loss
1.8 1.8
CH4 Output Current (A) CH6 Output Current vs. Power Loss
CH5 Power Loss (W)
CH6 Power Loss (W)
1.5 1.2 0.9
VIN=7.2 V Vo5=1.5 V
1.5 1.2 0.9
VIN=7.2 V Vo6=1.1 V/1.05 V
Vo6=1.1 V Vo6=1.05 V
Thermal design point
0.6 0.3 0 0 1 2 3 4 5
Thermal design point
0.6 0.3 0
0
1
2
3
4
5
CH5 Output Current (A)
CH6 Output Current (A)
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NOTES FOR UNCONNECTED PINS
1. PIN CONNECTION WHEN NOT USING CH1 or CH2
When CH1 or CH2 are not used, connect the PVDD pins to power supply, connect the PG pins, CTL pins and FB pins to Analog ground (AGND), leave OUTH pins, OUTL pins, CB pins and LX pins open and connect the PGND pins to Power ground. * CH1 is not used
PVDD1 OUT1H PG1
1
Power supply "OPEN" "OPEN" "OPEN" "OPEN"
CB1 LX1 OUT1L PGND1
CTL1 FB1
* CH2 is not used
PVDD2 OUT2H PG2
1
Power supply "OPEN" "OPEN" "OPEN" "OPEN"
CB2 LX2 OUT2L PGND2
CTL2 FB2
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2. PIN CONNECTION WHEN NOT USING CH3 and CH4
When CH3 and CH4 are not used, connect the PVDD pins to power supply, connect the FSEL4 pin, VSEL34 pin, PG pins, CTL34 pins and FB pins to Analog ground (AGND), leave CB pins and LX pins open and connect the PGND pins to Power ground. * CH3 and CH4 are not used
FSEL4 VSEL34 PG3 CTL34 FB3
PVDD3
Power supply
CB3 LX3
"OPEN" "OPEN"
PGND3 PVDD4
Power supply
PG4
CB4 LX4
"OPEN" "OPEN"
FB4 PGND4
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3. PIN CONNECTION WHEN NOT USING CH4, BUT USING CH3
When CH4 is not used but CH3 is used, connect the PVDD4 pins to VB pin through around 5 k resistor, connect the PG4 pin to Analog ground (AGND), connect 0.1 F capacitor between CB4 and LX4 pins and connect the PGND4 pin to Power ground, connect FSEL4 and FB4 pins to VREF pin. * CH4 is not used, but CH3 is used
VREF FSEL4 PVDD4
VB
around 5 k
CB4 0.1 F LX4
FB4
Control signal : "H"
CTL34 PG4
PGND4
Note : Both CH3 and CH4 become active when CTL34 is on. Connect the pins like shown up above when CH4 is not used but CH3 is used. PVDD4 must not be open.
4. PIN CONNECTION WHEN NOT USING CH5
When CH5 is not used, connect the PVDD5 pins to power supply, connect the PG5, CTL5 and FB5 pins to Analog ground (AGND), leave CB5 and LX5 pins open and connect the PGND5 pin to Power ground. * CH5 is not used
PVDD5
Power supply
PG5 CTL5 FB5
CB5 LX5
"OPEN" "OPEN"
PGND5
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5. PIN CONNECTION WHEN NOT USING CH6
When CH6 is not used, connect the PVDD6 pins to power supply, connect the PG6, CTL6, FB6 and DVSEL6 pins to Analog ground (AGND), leave CB6 and LX6 pins open and connect the PGND6 pin to Power ground. * CH6 is not used
PVDD6
Power supply
PG6 CTL6 FB6 DVSEL6
CB6 LX6
"OPEN" "OPEN"
PGND6
6. PIN CONNECTION WHEN NOT USING POWERGOOD FUNCTION
When the Power good function is not used, connect the PG pins or ALLPG pin to Analog ground (AGND). * PG or ALLPG are not used
PG
ALLPG
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MB39C308
APPLICATION NOTE
* Inductor Selection See the " RECOMMENDED OPERATING CONDITIONS" for the recommended inductance. Furthermore, to confirm whether the current flowing through the inductor is within the rated value, the maximum value of the current flowing through the inductor needs to be found. The maximum current flowing through the inductor can be found from the following formula. ILMAX IoMAX + VDD - VO L IL 2 VO VDD x fOSC
IL =
x
ILMAX : Maximum current through inductor [A] IoMAX : Maximum load current [A] IL VDD VO fOSC : Inductor ripple current peak-to-peak value [A] : Switching power supply voltage [V] : Output setting voltage [V] : Switching frequency [Hz]
Inductor current
ILMAX IoMAX
IL 0
Time
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* FET Selection (CH1, CH2) This IC operation requires the voltage which is generated between drain and source on the high-side FET. Set the on resistance of high-side FET within the below range for reference. CH1 high-side FET on resistance : 24 m to 40 m CH2 high-side FET on resistance : 12 m to 20 m The current limit value for over current protection (OCP) is determined by the high-side FET on resistance in use. The current limit value is obtained by the following formula. IO1_OCP = 0.141 RON1 0.133 RON2 - 0.5 L x fOSC 0.5 L x fOSC x (VDD - VO1) x VO1 VDD (VDD - VO2) x VO2 VDD
IO2_OCP = VDD VO RON L fOSC
-
x
: Switching system power supply voltage [V] : Output setting voltage [V] : High-side FET on resistance [] : Inductor value [H] : Switching frequency [Hz]
Also, 2.5 V drive products are recommended for the high-side FET. A bootstrap diode is recommended to connect to the high-side FET for the use of 4 V drive products (see "* Bootstrap Diode Selection" for the detail). In order to judge whether the electrical current flowing through the FET is within the rated value, the maximum value of the current flowing through the FET needs to be found. The maximum current flowing through the FET can be found from the following formula. IDMAX IoMAX + IL 2
IDMAX : Maximum value of FET drain current [A] IoMAX : Maximum load current [A] IL : Inductor ripple current peak-to-peak value [A]
Furthermore, in order to judge whether the power dissipation of the FET is within the rated value, the power dissipation of the FET needs to be found. The power dissipation of the high-side FET can be found from the following formula. PHisideFET = PRON + PSW PHisideFET : High-side FET power dissipation [W] PRON PSW : High-side FET conducting power dissipation [W] : High-side FET SW power dissipation [W]
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High-side FET conducting power dissipation PRON = (IoMAX) 2 x VO VDD x RON
PRON : High-side FET conducting power dissipation [W] IoMAX : Maximum load current [A] VDD VO RON : Switching system power supply voltage [V] : Output setting voltage [V] : High-side FET on resistance []
High-side FET switching power dissipation PSW = PSW VDD fOSC VDD x fOSC x (Ibtm x tr + Itop x tf) 2 : Switching power dissipation [W] : Switching system power supply voltage [V] : Switching frequency (Hz)
Ibtm : Inductor ripple current bottom value [A] Itop : Inductor ripple current top value [A] tr tf : High-side FET turn-on time [s] : High-side FET turn-off time [s]
tr and tf can be found simply from the following formula. tr = Qgd x 12 5 - Vth tf = Qgd x 12 Vth
Qgd : Gate-Drain charge of High-side FET [C] Vth : High-side FET threshold voltage [V] The power dissipation of the Low-side FET can be found from the following formula. PLosideFET = PRon = (IOMAX) 2 x (1 VO VDD ) x Ron
PRon : Low-side FET conducting power dissipation [W] IoMAX : Maximum load current [A] VDD VO Ron : Switching power supply voltage [V] : Output setting voltage [V] : Low-side FET on resistance []
Note : The transition voltage of the voltage between the drain and source of the Low-side FET is generally small and the switching power loss is negligible. Therefore it has been omitted from this formula.
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* Input Capacitor Selection Because this IC uses the C-Mode system, it is recommended to use ceramic capacitors with a small ESR. See the " RECOMMENDED OPERATING CONDITIONS" for the value of the capacitance. * Output Capacitor Selection Because this IC uses the C-Mode system, it is recommended to use ceramic capacitors with a small ESR. See the " RECOMMENDED OPERATING CONDITIONS" for the value of the capacitance. * Bootstrap Diode Selection It is not necessary to connect diode to the outside device normally because this device contains a bootstrap diode. However, it is recommended to add a shotkey barrier diode (SBD) when 4 V drive products is used for CH1 and CH2 switching FET. In this case, select the smallest forward current possible and connect as the figure below. * When adding bootstrap SBD to CH1
CB1
VB
The current to drive on the gate of high-side FET flows to the SBD of the bootstrap diode. The average current can be found by the following formula. However, set the current which does not exceed the maximum rating. ID Qg x fOSC ID Qg fOSC : Forward current [A] : Total gate electric charge of high-side FET [C] : Switching frequency [Hz]
The voltage rating of bootstrap capacitor can be found by the following formula. VR_BOOT > VDD VR_BOOT : Bootstrap diode DC reverse voltage [V] VDD : Switching power supply voltage [V]
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* Bootstrap Capacitor Selection Although the default bootstrap capacitor (the capacitor between CB and LX) is 0.1F, this may need to be adjusted if the FET used on CH1 and CH2 have a large Qg. The bootstrap capacitor needs to be able to charge sufficiently to drive the gate of the High-side FET. As a rough guide, select a capacitor with a minimum value of capacitance that is able to accumulate approximately 10 times the charge of the Qg of the High-side FET. CCB 10 x CCB Qg VCB Qg VCB
: Bootstrap capacitance [F] : High-side SWFET gate charge [C] : CB voltage (4.3 V)
* VB Capacitor Selection Although the default VB capacitor is 1 F, this may need to be adjusted if the FET used on CH1 and CH2 have a large Qg. The VB capacitor needs to be able to charge sufficiently to drive the gate of the High-side FET. As a rough guide, select a capacitor with a minimum value of capacitance that is able to accumulate approximately 50 times the charge of the Qg of the High-side FET. CVB 50 x CVB
(
VCB
+
VVB
: VB capacitance [F]
QgH12 : Total gate charge of High-side FET for CH1 and CH2 [C] (Total when Vgs = 4.3 V) QgL12 : Total gate charge of Low-side FET for CH1 and CH2 [C] (Total when Vgs = 5 V) VVB VCB : VB voltage (5 V) : CB voltage (4.3 V)
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(
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QgH12 + 9.3 x 10-9
QgL12 + 23 x 10-9
MB39C308
* Power Dissipation and Thermal Design Although these does not need to be examined in most cases because the IC is highly efficient, Dissipation and the thermal design may need to be investigate if the IC is used with high power supply voltages, high oscillator frequencies, high loads, or at high temperatures. The internal IC power dissipation (PIC) can be found from the following formula. PIC = VDD x (IDD + Qg12 + 32 x 10-9) x fOSC + PHisideFET3-6 + PLosideFET3-6 PIC VDD IDD Qg12 fOSC : Internal IC power dissipation [W] : Power supply voltage (VIN) [V] : Power supply current [A] (250 A Typ) : Total gate charge of High-side FET (VGS = 4.3 V) and Low-side FET (VGS = 5 V) for CH1 and CH2 [C] : Switching frequency [Hz]
PHisideFET3-6 : Total High-side SWFET power dissipation of internal High-side FET [W] PLosideFET3-6 : Total Low-side SWFET power dissipation of internal Low-side FET [W] Furthermore, the power dissipation of the High-side FET of each built-in channel can be found from the following formula. PHisideFET = PRON + PSW PHisideFET : High-side FET power dissipation [W] PRON PSW : High-side FET conducting power dissipation [W] : High-side FET switching power dissipation [W]
High-side FET conducting power dissipation PRON = (IoMAX) 2 VO VDD x RON
PRON : High-side FET conducting power dissipation [W] IoMAX : Maximum load current [A] VDD VO : Switching power supply voltage [V] : Output setting voltage [V]
RON : On resistance of High-side FET []
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High-side FET switching power dissipation PSW = VDD x fOSC x (Ibtm x tr + Itop x tf) 2
PSW : SW power dissipation [W] VDD : Switching system power supply voltage [V] fOSC : Oscillation frequency (Hz) Ibtm : Inductor ripple current bottom value [A] Itop : Inductor ripple current top value [A] tr tf : High-side FET turn-on time [s] : High-side FET turn-off time [s]
tr and tf are simply given by the following values. tr = 4 ns tf = 4 ns
The power dissipation of the Low-side FET can be found from the following formula. PRon = (IOMAX)2 x (1 - VO VDD ) x Ron
PRon : Low-side FET conducting power dissipation [W] IoMAX : Maximum load current [A] VDD VO Ron : Switching system power supply voltage [V] : Output setting voltage [V] : Low-side FET on resistance []
Note : The transition voltage of the voltage between the drain and source of the Low-side FET is generally small and the switching power loss is negligible. Therefore it has been omitted from this formula. The junction temperature (Tj) can be found from the following formula. Tj = Ta + ja x PIC Tj : Junction temperature [ C] ( + 125 C Max) Ta : Ambient temperature [ C] ja : PFBGA-208 package thermal resistance (34 C/W) PIC : IC power dissipation [W]
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REFERENCE DATA
* Efficiency vs. load current
100
CH1 1 - IO1
100
CH2 2 - IO2
efficiency 2 (%)
efficiency 1 (%)
95 90 85 80 75 70 65 60 0.01 0.1 1 10
95 90 85 80 75 70 65 60 0.01 0.1 1 10
Load current IO1 (A)
Load current IO2 (A)
100 95
CH3 3 - IO3
Vo3 = 1.8 V Vo3 = 1.5 V
100 95
CH4 4 - IO4
fosc = 700 kHz, VO4 = 0.9 V fosc = 700 kHz, VO4 = 0.75 V fosc = 350 kHz, VO4 = 0.9 V fosc = 350 kHz, VO4 = 0.75 V
efficiency 4 (%)
efficiency 3 (%)
90 85 80 75 70 65 60 0.01 0.1 1 10
90 85 80 75 70 65 60 0.01
0.1
1
10
Load current IO3 (A)
Load current IO4 (A)
100 95
CH5 5 - IO5
100 95
CH6 6 - IO6
VO6 = 1.05 V VO6 = 1.1 V
efficiency 5 (%)
90 85 80 75 70 65 60 0.01 0.1 1 10
efficiency 6 (%)
90 85 80 75 70 65 60 0.01 0.1 1 10
Load current IO5 (A)
Load current IO6 (A)
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* Load regulation
CH1 VO1 vs. IO1
CH2 VO2 vs. IO2
Output voltage VO1 (V)
Output voltage VO2 (V)
Ta = + 25C VO1 = 5.0 V fosc = 700 kHz
Ta = + 25C VO2 = 3.3 V fosc = 700 kHz
Load current IO1 (A)
Load current IO2 (A)
CH3 VO3 vs. IO3
CH3 VO3 vs. IO3
Output voltage VO3 (V)
Output voltage VO3 (V)
Ta = + 25C VO3 = 1.5 V fosc = 700 kHz
Ta = + 25C VO3 = 1.8 V fosc = 700 kHz
Load current IO3 (A)
Load current IO3 (A)
CH4 VO4 vs. IO4
fosc = 350 kHz fosc = 700 kHz
CH4 VO4 vs. IO4
fosc = 350 kHz fosc = 700 kHz
Output voltage VO4 (V)
Output voltage VO4 (V)
Ta = + 25C VO4 = 0.75 V
Ta = + 25C VO4 = 0.9 V
Load current IO4 (A)
Load current IO4 (A) (Continued)
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* Line regulation
CH1 VO1 vs. VIN
CH2 VO2 vs. VIN
Output voltage VO1 (V)
Output voltage VO2 (V)
Ta = + 25C VO1 = 5.0 V fosc = 700 kHz
Ta = + 25C VO2 = 3.3 V fosc = 700 kHz
Input voltage VIN (V)
Input voltage VIN (V)
CH3 VO3 vs. VIN
CH3 VO3 vs. VIN
Output voltage VO3 (V)
Output voltage VO3 (V)
Ta = + 25C VO3 = 1.5 V fosc = 700 kHz
Ta = + 25C VO3 = 1.8 V fosc = 700 kHz
Input voltage VIN (V)
Input voltage VIN (V)
CH4 VO4 vs. VIN
fosc = 350 kHz fosc = 700 kHz
CH4 VO4 vs. VIN
fosc = 350 kHz fosc = 700 kHz
Output voltage VO4 (V)
Ta = + 25C VO4 = 0.75 V
Output voltage VO4 (V)
Ta = + 25C VO4 = 0.9 V
Input voltage VIN (V)
Input voltage VIN (V) (Continued)
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(Continued)
CH5 VO5 vs. VIN
Output voltage VO5 (V)
Ta = + 25C VO5 = 1.5 V fosc = 700 kHz
Input voltage VIN (V)
CH6 VO6 vs. VIN
CH6 VO6 vs. VIN
Output voltage VO6 (V)
Output voltage VO6 (V)
Ta = + 25C VO6 = 1.05 V fosc = 700 kHz
Ta = + 25C VO6 = 1.1 V fosc = 700 kHz
Input voltage VIN (V)
Input voltage VIN (V)
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* Waveforms at load step response
CH1 (VO1 = 5.0 V) IO1 = 0 A 2 A, IO1 slew rate = 2 A/s Ta = + 25 C VIN = 7.2 V VO1 = 5.0 V fosc = 700 kHz
4
CH2 (VO2 = 3.3 V) IO2 = 0 A 4.5 A, IO2 slew rate = 4.5 A/s Ta = + 25 C VIN = 7.2 V VO2 = 3.3 V fosc = 700 kHz
IO2 2 A/div
4
IO1 2A/div
VO1 500 mV/div 5V
1
VO2 500 mV/div 3.3 V 1 100 s/div 100 s/div
CH3 (VO3 = 1.5 V) IO3 = 0 A 2.7 A, IO3 slew rate = 2.7 A/s Ta = + 25 C VIN = 7.2 V VO3 = 1.5 V fosc = 700 kHz
4
CH3 (VO3 = 1.8 V) IO3 = 0 A 2.7 A, IO3 slew rate = 2.7 A/s Ta = + 25 C VIN = 7.2 V VO3 = 1.8 V fosc = 700 kHz
IO3 1 A/div
IO3 1 A/div
4
VO3 200 mV/div 1.5 V
1
VO3 200 mV/div 1.8 V 100 s/div
1
100 s/div
CH4 (fosc = 350 kHz, VO4 = 0.75 V) IO4 = 0 A 1.5 A, IO4 slew rate = 1.5 A/s Ta = + 25 C VIN = 7.2 V VO4 = 0.75 V fosc = 350 kHz
4
CH4 (fosc = 350 kHz, VO4 = 0.9 V) 1.5 A, IO4 slew rate = 1.5 A/s IO4 = 0 A Ta = + 25 C VIN = 7.2 V VO4 = 0.9 V fosc = 350 kHz IO4 1 A/div
4
IO4 1 A/div
VO4 100 mV/div 0.75 V
1
VO4 100 mV/div 0.9 V 100 s/div
1
100 s/div
(Continued) 42 DS04-27261-6E
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(Continued)
CH4 (fosc = 700 kHz, VO4 = 0.75 V) IO4 = 0 A 1.5 A, IO4 slew rate = 1.5 A/s Ta = + 25 C VIN = 7.2 V VO4 = 0.75 V fosc = 700 kHz
4
CH4 (fosc = 700 kHz, VO4 = 0.9 V) IO4 = 0 A 1.5 A, IO4 slew rate = 1.5 A/s Ta = + 25 C VIN = 7.2 V VO4 = 0.9 V fosc = 700 kHz
4
IO4 1 A/div
IO4 1 A/div
VO4 100 mV/div 0.75 V
1
VO4 100 mV/div 0.9 V 100 s/div
1
100 s/div
CH5 (VO5 = 1.5 V) IO5 = 0 A 2.5 A, IO5 slew rate = 2.5 A/s Ta = + 25 C VIN = 7.2 V VO5 = 1.5 V fosc = 700 kHz
4
IO5 1 A/div
VO5 200 mV/div 1.5 V
1
100 s/div
CH6 (VO6 = 1.05 V) IO6 = 0 A 3.5 A, IO6 slew rate = 3.5 A/s Ta = + 25 C VIN = 7.2 V VO6 = 1.05 V fosc = 700 kHz
4
CH6 (VO6 = 1.1 V) IO6 = 0 A 3.5 A, IO6 slew rate = 3.5 A/s Ta = + 25 C VIN = 7.2 V VO6 = 1.1 V fosc = 700 kHz
IO6 2 A/div
4
IO6 2 A/div
VO6 100 mV/div
VO6 100 mV/div
1.05 V 1 100 s/div
1.1 V
1
100 s/div
DS04-27261-6E
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MB39C308
* Waveform at Soft-start and Soft-stop
CH1
CH2
1
1
CTL1:2 V/div
Ta = + 25 C VIN = 7.2 V VO1 = 5.0 V IO1 = 2 A fosc = 700 kHz
CTL2:2 V/div
Ta = + 25 C VIN = 7.2 V VO2 = 3.3 V IO2 = 4.5 A fosc = 700 kHz
2
VO1: 2 V/div 5 ms/div
2
VO2: 2 V/div 5 ms/div
CH3, CH4
CH5
1
1
CTL34:2 V/div
VO3: 500 mv/div
2
Ta = + 25 C VIN = 7.2 V VO3 = 1.8 V IO3 = 2.7 A VO4 = 0.9 V IO4 = 1.5 A fosc = 700 kHz
CTL5:2 V/div
Ta = + 25 C VIN = 7.2 V VO5 = 1.5 V IO5 = 2.5 A fosc = 700 kHz
3
2
VO4: 500 mV/div 5 ms/div
VO5: 500 mV/div 5 ms/div
CH6
1
CTL6:2 V/div
Ta = + 25 C VIN = 7.2 V VO6 = 1.05 V IO6 = 3.5 A fosc = 700 kHz
2
VO6:500 mV/div 5 ms/div
44
DS04-27261-6E
MB39C308
(Continued)
VB
100 k
R5
M1 MB39C308PFBGA208 F14 C13 PG5 CTL5 PVDD5A PVDD5B PVDD5C PVDD5D PVDD5E PVDD5F PVDD5G PVDD5H CB5 LX5A LX5B LX5C LX5D LX5E LX5F LX5G LX5H LX5I PGND5A PGND5B PGND5C PGND5D PGND5E PGND5F PGND5G PGND5H PGND5I L1 M3 M2 M1 N3 N2 N1 P1 L2
4.7 F
VIN
PG5 CTL5 VO5
L3
FB5
C17 L5 1.5 H
100 F C5
H3 0.1 F H2 H1 J3 J2 J1 K3 K2 K1 E3 E2 E1 F3 F2 F1 G3 G2 G1
VO5 Vo5s Vo5
VB
100 k
R6
VIN E14 B13 PG6 CTL6 PVDD6A PVDD6B PVDD6C PVDD6D PVDD6E PVDD6F PVDD6G PVDD6H PVDD6I PVDD6J CB6 LX6A LX6B LX6C LX6D LX6E LX6F LX6G LX6H LX6I LX6J PGND6A PGND6B PGND6C PGND6D PGND6E PGND6F PGND6G PGND6H PGND6I PGND6J A10 A9 A8 A7 B10 B9 B8 B7 C9 C8 C7 A6 A5 A4 B6 B5 B4 C6 C5 C4 C3 A3 A2 B3 B2 B1 C2 C1 D3 D2 D1 VIN D14
1 F
4.7 F
PG6 CTL6
DVSEL6 VO6
B11 C10
DVSEL6 FB6
C18 0.1 F L6 1.5 H
100 F C6-1 100 F C6-2
VO6 Vo6s Vo6
M1 MB39C308PFBGA208 E7 Thermal1 E8 Thermal2 E9 Thermal3 E10 Thermal4 F6 Thermal5 F7 Thermal6 F8 Thermal7 F9 F10 Thermal8 Thermal9 F11 Thermal10 G5 Thermal11 G6 Thermal12 G7 Thermal13 G8 Thermal14 G9 Thermal15 G10 Thermal16 G11 Thermal17 G12 Thermal18 H5 Thermal19 H6 Thermal20 H7 Thermal21 H8 Thermal22 H9 Thermal23 H10 Thermal24 H11 Thermal25 H12 Thermal26 J5 Thermal27 J6 Thermal28 J7 Thermal29 J8 Thermal30 J9 Thermal31 J10 Thermal32 J11 Thermal33 J12 Thermal34 K5 Thermal35 K6 Thermal36 K7 Thermal37 K8 Thermal38 K9 Thermal39 K10 Thermal40 K11 Thermal41 K12 Thermal42 L6 Thermal43 L7 Thermal44 L8 Thermal45 L9 Thermal46 L10 Thermal47 L11 Thermal48 M7 Thermal49 M8 Thermal50 M9 Thermal51 M10 Thermal52
C12
C11
AGND
VB
100 k
R7
ALLPG
ALLPG
AVDD A15 AGND B14
C19 C20
VB B16 SS1
VIN
1 F
PVDD7 A11 PGND7 A13
VB
1 F
B15
SS2
VB A12 DIN VREF B12 A14
4.7 F C22 C21
VB
VREF VREF
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MB39C308
PARTS LIST
Symbol M1 Q1 Part name IC N-ch Dual MOSFET Model name MB39C308 ECH8607 Specification VDS = 30 V, ID = 5 A (Max) VDS = 20 V, ID = 5.7 A (Max) VDS = 20 V, ID = 5.7 A (Max) 100 k 100 k 100 k 100 k 100 k 100 k 100 k Pattern short Pattern short 100 F (6.3 V) 100 F (6.3 V) 100 F (4 V) 100 F (4 V) 100 F (4 V) 100 F (4 V) 100 F (4 V) 4.7 F (16 V) 4.7 F (16 V) 4.7 F (16 V) 4.7 F (16 V) 4.7 F (16 V) 4.7 F (16 V) Package PFBGA-208 ECH8 Vendor FML SANYO Remarks Ch1 High & Low-side Ch2 High-side Ch2 Low-side (Ch2 High-side) (Ch2 Low-side) PG PG PG PG PG PG PG VSEL34 FSEL4 VO VO VO VO VO VO VO PVDD PVDD PVDD PVDD PVDD PVDD (Continued) DS04-27261-6E 47
Q2-1
N-ch MOSFET
FDMA420NZ
MLP2x2-6L
FAIRCHILD FAIRCHILD SSM SSM SSM SSM SSM SSM SSM TDK TDK MURATA MURATA MURATA MURATA MURATA TDK TDK TDK TDK TDK TDK
Q3-1
N-ch MOSFET
FDMA420NZ RR0816P-104-D RR0816P-104-D RR0816P-104-D RR0816P-104-D RR0816P-104-D RR0816P-104-D RR0816P-104-D C3225JB0J107M C3225JB0J107M GRM31CR60G107ME39L GRM31CR60G107ME39L GRM31CR60G107ME39L GRM31CR60G107ME39L GRM31CR60G107ME39L C2012JB1C475K C2012JB1C475K C2012JB1C475K C2012JB1C475K C2012JB1C475K C2012JB1C475K
MLP2x2-6L
Q2-2 Q3-2 R1 R2 R3 R4 R5 R6 R7 R8 R9 C1 C2 C3 C4 C5 C6-1 C6-2 C7 C8 C9 C10 C11 C12
N-ch MOSFET N-ch MOSFET Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor
SOT-6 TSOP-6 1608 1608 1608 1608 1608 1608 1608 3225 3225 3216 3216 3216 3216 3216 2012 2012 2012 2012 2012 2012
MB39C308
(Continued) Symbol C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 L1 L2 L3 L4 L5 L6 PIN FML SANYO FAIRCHILD SSM TDK MURATA NEC TOKIN Mac-Eight
Part name
Model name C1608JB1E224K C1608JB1E224K C1608JB1H104K C1608JB1H104K C1608JB1H104K C1608JB1H104K C1608JB1C105K C1608JB1C105K C1608JB1C105K C1608JB1A475K RLF7030-3R3M4R1 MPLC0730L3R3 RLF7030-1R5N6R1 RLF7030-1R5N6R1 RLF7030-1R5N6R1 RLF7030-1R5N6R1 WT-2-1
Specification 0.22 F (25 V) 0.22 F (25 V) 0.1 F (50 V) 0.1 F (50 V) 0.1 F (50 V) 0.1 F (50 V) 1 F (16 V) 1 F (16 V) 1 F (16 V) 4.7 F (10 V) 3.3 H (4.1 A) 3.3 H (5.7 A) 1.5 H (6.1 A) 1.5 H (6.1 A) 1.5 H (6.1 A) 1.5 H (6.1 A)
Package 1608 1608 1608 1608 1608 1608 1608 1608 1608 1608 SMD SMD SMD SMD SMD SMD
Vendor TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK TDK NEC TOKIN TDK TDK TDK TDK Mac-Eight
Remarks CB CB CB CB CB CB AVDD PVDD7 VB VREF
Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Inductor Inductor Inductor Inductor Inductor Inductor Wiring Terminal
: FUJITSU MICROELECTRONICS LIMITED : SANYO Electric Co.,Ltd. : Fairchild Semiconductor Japan Ltd. : SUSUMU Co., Ltd : TDK Corporation : Murata Manufacturing Co., Ltd. : NEC TOKIN Corporation : Mac-Eight Co.,Ltd.
48
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MB39C308
PRINTED CIRCUIT BOARD LAYOUT
Design of the PCB layout is important to make the suitable operation, suppressing noise or high efficiency ratio. Refer to the evaluation board layout of MB39C308EVB-01 and consider the following guideline when designing the layout of a circuit board.
1. Common items for each channel and peripheral components
* Ground and design for radiation of heat At least, place the GND layer (PGND) in one of PCB internal layers. Place the through holes next to the GND pin of IC and each component, and connect them to the GND layer with low impedance. Place the AGND which is separated from the GND layer with flowing large current if possible. Connect the bypass-capacitors of VREF and AVDD and the AGND pin of IC to the AGND. Connect AGND pin of IC to the GND layer by one point connection as close as possible so as not to flow a large current to the AGND. Connect GND pins of VB bypass-capacitor and the switching components to the GND layer directly. Connect each thermal pin to the GND layer via the through hole so that the heat can be dissipated efficiency. It is an ideal to place a through hole on a pad in the footprint of each thermal pin. Furthermore, it is also effective to place the GND plane on the back side of the substrate of the trace mounted on IC. * Bypass capacitors and boot strap capacitors Place the bypass-capacitors connected to the VREF, AVDD, VB, PVDD7 pins next to each pin of IC. Furthermore, connect the bypass-capacitors with the shortest path on surface layer to each pin. Place GND pins of bypasscapacitors connected to VB and PVDD7 pins to the PGND7 pin with the shortest path. Place the bootstrap capacitors for each channel next to CBx and LXx pins. * Example layout
MB39C308
CBx LXx AVDD VREF
Pad of IC Through hole Capacitor
VB PVDD7
x : Number of each channel
* Feedback line Place the feed back lines to FB pins for each channel away from switching components and lines, because the feed back line is sensitive to noise.
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MB39C308
* Printed circuit board design rule for PFBGA
SMD
Solder-mask opening
NSMD
Solder-mask opening
Pad pattern
SMD (solder-mask defined) Pad pattern 0.5 mm pitch 0.325 to 0.35 Solder-mask opening 0.225 to 0.25
NSMD (non-solder mask defined) Pad pattern 0.225 to 0.25 Solder-mask opening 0.325 to 0.35
50
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MB39C308
2. External switching FET channel (CH1, CH2)
For the loop consisting of the input capacitor (CIN), high-side FET and low-side FET of each channel, take the most care of making the current loop as tight as possible. The input capacitor (CIN), high-side FET and low-side FET, inductor (L) and output capacitor (CO) should be connected to the surface layer as much as possible using short and thick connections. In addition, avoid making connections to theses components via the through hole. Large transient current flows through the connections between the FET gate and OUT1H,OUT1L,OUT2H and OUT2L pins. Make this lines as short and thick as possible (ex. 0.5 mm width). PVDD1, PVDD2, LX1, LX2 pins sense the voltage between drain and source at high-side FET. Connect the PVDD1 or PVDD2 pin to the drain pin of high-side FET directly. Avoid connecting to the other part on the line. Connect the LX1 or LX2 pin to the source pin of high-side FET directly. Connect the bootstrap capacitor as in the following graph and avoid connecting to the other part on the line. Furthermore, large transient current also flows through the connection to the LX pin. Make the line as short and thick as possible (exp: PVDD1, PVDD2, LX1, LX2 lines are 0.5 mm width). When not connecting the PVDD and the LX pins to the drain or the source pin of the high-side FET as the layout below, an error may occur in PWM/PFM switch current value and the OCP setting value because of the error occurred in the current sense value. * Example layout
MB39C308
CB1, CB2 pin PVDD1, PVDD2 pin LX1, LX2 pin
Connect the PVDD pin to the drain pin of high-side FET directly so as to sense the drain voltage at highside FET. The line shouldn't be connected to the other parts.
Drain pad
VIN
High-side FET
Bootstrap capacitor
Through hole
CIN
PGND
Source pad
Low-side FET
CO L
Loop
VO
Connect the LX pin to the source pin of highside FET directly so as to sense the source voltage at high-side FET. The line shouldn't be connected to the other parts except the bootstrap capacitor.
To FB1,FB2 pin
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MB39C308
3. Internal switching FET channel (CH3 to CH6)
Place the input capacitor (CIN) for each channel next to PVDDx and PGNDx pins as in the following graph. The PVDDx, LXx, PGNDx pins, input capacitor (CIN), inductor (L) and output capacitor (CO) should be connected to the surface layer as much as possible using short and thick connections. Avoid connecting these components via the through hole. * Example layout
MB39C308
VIN
PVDDx pin LXx pin PGNDx pin
PGND CO VO
CIN
L
x : Number of channel
Through hole
To FBx pin
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MB39C308
USAGE PRECAUTION
1. Do not configure the IC over the maximum ratings
lf the lC is used over the maximum ratings, the LSl may be permanently damaged. It is preferable for the device to normally operate within the recommended usage conditions. Usage outside of these conditions can have a bad effect on the reliability of the LSI.
2. Use the devices within recommended operating conditions
The recommended operating conditions are under which the LSl is guaranteed to operate. The electrical ratings are guaranteed when the device is used within the recommended operating conditions and under the conditions stated for each item.
3. Printed circuit board ground lines should be set up with consideration for common impedance 4. Take appropriate measures against static electricity
* * * * Containers for semiconductor materials should have anti-static protection or be made of conductive material. After mounting, printed circuit boards should be stored and shipped in conductive bags or containers. Work platforms, tools, and instruments should be properly grounded. Working personnel should be grounded with resistance of 250 k to 1 M between body and ground.
5. Do not apply negative voltages
The use of negative voltages below -0.3 V may create parasitic transistors on LSI lines, which can cause malfunctions.
6. Warnings when connecting the load
During DC/DC operation, if the output is connected by hard switching to a capacitance that greatly exceeds the DC/DC output capacitance, the output voltage may oscillate and the protection function may be detected due to the instant voltage drop. Take note of the following points. * Connecting to the load capacitor A P-ch FET is normally used as a load switch, and a gate resistor is inserted as shown below for the switch to turn on gradually and to prevent rush current.
VO
Load Capacitor
Load switch
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MB39C308
ORDERING INFORMATION
Part number MB39C308BGF Package 208-ball plastic PFBGA (BGA-208P-M02) Remarks
EV BOARD ORDERING INFORMATION
EV board part No. MB39C308EVB-11 EV board version No. Board rev.1.0 Remarks PFBGA-208
RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of Fujitsu Microelectronics with "E1" are compliant with RoHS Directive , and has observed the standard of lead, cadmium, mercury, hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl ethers (PBDE) . A product whose part number has trailing characters "E1" is RoHS compliant.
MARKING FORMAT (LEAD FREE VERSION)
J APAN MB 39 C308 XXXX XXX E1
Lead-free version
INDEX
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MB39C308
MB39C308BGF RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
[Fujitsu Microelectronics Recommended Mounting Conditions] Item Condition Mounting Method Mounting times Before opening Storage period From opening to the 2nd reflow When the storage period after opening was exceeded Storage conditions IR (infrared reflow) , Manual soldering (partial heating method) 2 times Please use it within two years after Manufacture. Less than 6 days Please processes within 6 days after baking (125 C, 24H)
5 C to 30 C, 70%RH or less (the lowest possible humidity)
[Temperature Profile for FJ Standard IR Reflow] (1) IR (infrared reflow) M rank : 250 C Max
250 C 245 C
Main heating
170 C to 190 C
RT
(b)
(c)
(d)
(e)
(a)
(d')
(a) Temperature Increase gradient (b) Preliminary heating (c) Temperature Increase gradient (d) Actual heating (d')
(e) Cooling
: Average 1 C/s to 4 C/s : Temperature 170 C to 190 C, 60 s to 180 s : Average 1 C/s to 4 C/s : Temperature 250 C Max; 245 C or more, 10 s or less : Temperature 230 C or more, 40 s or less or Temperature 225 C or more, 60 s or less or Temperature 220 C or more, 80 s or less : Natural cooling or forced cooling
Note : Temperature : the top of the package body (2) Manual soldering (partial heating method) Conditions : Temperature 400 C Max Times : 5 s max/pin 57
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CONTENTS
page DESCRIPTION .................................................................................................................................................... 1 FEATURES .......................................................................................................................................................... 1 APPLICATIONS .................................................................................................................................................. 2 PIN ASSIGNMENT ............................................................................................................................................. 3 PIN DESCRIPTIONS .......................................................................................................................................... 4 BLOCK DIAGRAM .............................................................................................................................................. 7 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 9 RECOMMENDED OPERATING CONDITIONS ............................................................................................ 10 ELECTRICAL CHARACTERISTICS ................................................................................................................ 12 CHANNEL CONTROL FUNCTION .................................................................................................................. 19 POWER GOOD FUNCTION ............................................................................................................................. 19 PROTECTION ..................................................................................................................................................... 20 DESCRIPTION OF SOFT-START AND SOFT-STOP OPERATION ......................................................... 21 PRESET FUNCTION OF CH3/CH4/CH6 OUTPUT VOLTAGE .................................................................. 23 TYPICAL CHARACTERISTICS ........................................................................................................................ 24 NOTES FOR UNCONNECTED PINS ............................................................................................................. 26 APPLICATION NOTE ......................................................................................................................................... 30 REFERENCE DATA ........................................................................................................................................... 37 TYPICAL APPLICATION CIRCUIT .................................................................................................................. 45 PARTS LIST ......................................................................................................................................................... 47 PRINTED CIRCUIT BOARD LAYOUT ............................................................................................................ 49 USAGE PRECAUTION ...................................................................................................................................... 53 ORDERING INFORMATION ............................................................................................................................. 55 EV BOARD ORDERING INFORMATION ....................................................................................................... 55 RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION .................................................. 55 MARKING FORMAT (LEAD FREE VERSION) .............................................................................................. 55 LABELING SAMPLE (LEAD FREE VERSION) ............................................................................................. 56 MB39C308BGF RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL .................... 57 PACKAGE DIMENSION .................................................................................................................................... 58
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MB39C308
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department

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